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LPC47N252
ADVANCE INFORMATION
Advanced Notebook I/O Controller with On-Board FLASH
FEATURES
3.3V Operation with 5V Tolerant Buffers ACPI 1.1, PC99/PC2001 Compliant LPC Interface with Clock Run Support - Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems - 15 Direct IRQs - Four 8-Bit DMA Channels - ACPI SCI Interface - nSMI - Shadowed write only registers Internal 64K Flash ROM - Programmed From Direct Parallel Interface, 8051, or LPC Host - 2k-Byte Lockable Boot Block - Can be Programmed Without 8051 Intervention Three Power Planes - Low Standby Current in Sleep Mode - Intelligent Auto Power Management for Super I/O ACPI Embedded Controller Interface Configuration Register Set Compatible with ISA Plug-and-Play Standard (Version 1.0a) High-Performance Embedded 8051 Keyboard and System Controller - Provides System Power Management - System Watch Dog Timer (WDT) - 8042 Style Host Interface - Supports Interrupt and Polling Access - 256 Bytes Data RAM - On-Chip Memory-Mapped Control Registers - Access to RTC and CMOS Registers - Up to 16x8 Keyboard Scan Matrix - Two 16 Bit Timer/Counters - Integrated Full-Duplex Serial Port Interface - Eleven 8051 Interrupt Sources - Thirty-Two 8-Bit, Host/8051 Mailbox Registers - Thirty-six Maskable Hardware Wake-Up Events - Fast GATEA20 - - Fast CPU_RESET Multiple Clock Sources and Operating Frequencies - IDLE and SLEEP Modes - Fail-Safe Ring Oscillator Advanced Infrared Communications Controller (IrCC 2.0) - IrDA V1.2 (4Mbps), HPSIR, ASKIR, Consumer IR Support - Two IR Ports - Relocatable Base I/O Address Real-Time Clock - MC146818 and DS1287 Compatible - 256 Bytes of Battery Backed CMOS in Two 128-Byte Banks - 128 Bytes of CMOS RAM Lockable in 4x32 Byte Blocks - 12 and 24 Hour Time Format - Binary and BCD Format - <2A Standby Current (typ) Two 8584-Style ACCESS.Bus Controllers - 8051 Controlled Logic Allows ACCESS.Bus Master or Slave Operation - ACCESS.Bus Controllers are Fully Operational on Standby Power - 2 Sets of Dedicated Pins per ACCESS.Bus Controller Four independent Hardware Driven PS/2 Ports 83 General Purpose I/O Pins - 36 Maskable Hardware Wake-Event Capable - 18 Programmable Open-Drain/Push-Pull Outputs - 16 Mapped into 8051 SFR Space - 24 LPC/8051-Addressable Three Programmable Pulse-Width Modulator Outputs - Independent Clock Rates - 6 Bit Duty Cycle Granularity - VCC1 and VCC2 operation mode Dual Fan Tachometer Inputs
SMSC DB - LPC47N252
Rev. 10/27/2000
2.88MB Super I/O Floppy Disk Controller - Relocatable to 480 Different Base I/O Addresses - 15 IRQ Options - 4 DMA Options - Open-Drain/Push-Pull Configurable Output Drivers - Licensed CMOS 765B Floppy Disk Controller - Advanced Digital Data Separator - Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core - Low Power CMOS Design with Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption - Supports Two Floppy Drives on the FDD Interface and Two Floppy Drives on the Parallel Port Interface - 12 mA FDD Interface Cable Drivers with Schmitt Trigger Inputs Licensed CMOS 765B Floppy Disk Controller Core - Supports Vertical Recording Format - 16-Byte Data FIFO - 100% IBM Compatibility - Detects All Overrun and Underrun Conditions - 12 mA Drivers and Schmitt Trigger Inputs - DMA Enable Logic - Data Rate and Drive Control Registers Enhanced Digital Data Separator - Low Cost Implementation
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No Filter Components Required 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes Multi-Mode Parallel Port with ChiProtect - Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bi-directional Parallel Port - Enhanced Parallel Port EPP 1.7 and EPP 1.9 Compatible (IEEE 1284 Compliant) - IEEE 1284 Compliant Enhanced Capabilities Port (ECP) - ChiProtect Circuitry to Prevent Printer Power-On Damage - Relocatable to 480 Different Base I/O Addresses - 15 IRQ Options - 4 DMA Options - Microsoft and HP compatible High Speed Mode - Floppy Disk Interface on Parallel Port - 8051-Controlled Parallel Port Mode Serial Port - High-Speed NS16550A-Compatible UART with 16-Byte Send/Receive FIFOs - Programmable Baud Rate Generator - Modem Control Circuitry Including 230k and 460k Baud - Relocatable to 480 Different Base I/O Addresses - 15 IRQ Options 208 Pin TQFP and FBGA Package Options
ORDERING INFORMATION
Order Numbers: LPC47N252-SG for 208 Pin FBGA Package LPC47N252-SD for 208 Pin TQFP Package
SMSC DB - LPC47N252
Page 2
Rev. 10/27/2000
GENERAL DESCRIPTION
The LPC47N252 is a 208-pin 3.3V LPC-based ACPI 1.1 and PC99/PC2001 compliant Notebook I/O Controller with Fast Infrared for mobile applications. The LPC47N252 incorporates a high-performance 8051-based keyboard controller; a 64k byte internal Flash ROM, four PS/2 ports; a real-time clock; SMSC's true CMOS 765B floppy disk controller with advanced digital data separator and 16-byte data FIFO; an NS16C550A-compatible UART, SMSC's advanced Infrared Communications Controller (IrCC 2.0) with a UART and a Synchronous Communications Engine to provide IrDA v1.1 (Fast IR) capabilities; one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support; two 8584-style Access Bus controllers with two Sets of Dedicated Pins per ACCESS.Bus Controller; a Serial IRQ peripheral agent interface; an ACPI Embedded Controller Interface; General Purpose I/O pins including eight pass through ports; three independently programmable pulse width modulators; two-floppy direct drive support; and maskable hardware wakeup events. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. The parallel port is compatible with IBM PC/AT architecture, as well as EPP and ECP. The 8051 controller can also take control of the parallel port interface to provide remote diagnostics or "Flashing" of the Flash memory. The LPC47N252 has three separate power planes to provide "instant on" and system power management functions. Additionally, the LPC47N252 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. Wake-up events and ACPI-related functions are supported through the SCI Interface. The LPC47N252's configuration register set is compatible with the ISA Plug-and-Play Standard (Version 1.0a) and provides the functionality to support Windows '95.The legacy host Super I/O Configuration and Alternate Super I/O Configuration decode ranges comply with the Low Pin Count Interface Specification, Revision 1.0. Through internal configuration registers, each of the LPC47N252's logical device's I/O address, DMA channel and IRQ channel may be programmed. There are 480 I/O address location options, 15 IRQ options, and four DMA channel options for each logical device. The LPC47N252 does not require any external filter components and is, therefore, easy to use and offers lower system cost and reduced board area. The LPC47N252 is software and register compatible with SMSC's proprietary 82077AA core.
(c) STANDARD MICROSYSTEMS CORPORATION (SMSC) 2000
80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123
Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC, ChiProtect, Ultra I/O and Multi-Mode are trademarks of Standard Microsystems Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC DB - LPC47N252
Page 3
Rev. 10/27/2000
MODE OUT6 VCC2 DRVDEN0 DRVDEN1 nMTR0 VSS nDS0 nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA nDSKCHG FPD IRTX IRRX KSO13 KSO12 KSO11 KSO10 KSO9 KSO8 KSO7 VCC1 KSO6 KSO5 KSO4 KSO3 KSO2 KSO1 KSO0 KSI7 KSI6 KSI5 KSI4 KSI3 KSI2 KSI1 KSI0 GPIO20 GPIO21 IMCLK IMDAT VSS KCLK KDAT EMCLK
SMSC DB - LPC47N252
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
LPC47N252 208 PIN TQFP
FIGURE 1 - LPC47N252 PIN CONFIGURATION
Page 4
EMDAT SGPIO30 SGPIO31 SGPIO32 SGPIO33 SGPIO34 SGPIO35 SGPIO36 SGPIO37 VCC1 SGPIO41 SGPIO42 SGPIO43 SGPIO44 SGPIO45 SGPIO46 SGPIO47 OUT0 OUT1 OUT2 VSS OUT3 OUT4 LGPIO50 LGPIO51 LGPIO52 LGPIO53 LGPIO54 LGPIO55 LGPIO56 VCC1 LGPIO57 LGPIO60 LGPIO61 LGPIO62 LGPIO63 VSS LGPIO64 LPCPD# LAD[0] LAD[1] LAD[2] LAD[3] LDRQ# LFRAME# LRESET# PCI_CLK nCLKRUN SER_IRQ nRESET_OUT CLOCKI VCC2 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VCC0 IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 GPIO12 GPIO11 GPIO10 GPIO13 VCC1 GPIO9 GPIO8 GPIO14 GPIO15 nRI nDCD nDTR nCTS nRTS nDSR VSS TXD RXD nSTROBE nALF nERROR nINIT nSLCTIN PD0 PD1 PD2 PD3 VCC2 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT PWRGD nPWR_LED VCC1_PWRGD 32kHz_OUT VSS nEC_SCI 24MHz_OUT
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
GPIO19 SGPIO40 GPIO17 VCC1 GPIO16 OUT7 OUT8 OUT9 OUT10 OUT11 nFDD_LED nBAT_LED AB1A_CLK AB1A_DATA OUT5 nEA VSS GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 VSS nFWP TEST_PIN VCC2 nDMS_LED FDC_nPP AB1B_CLK VCC1 AB1B_DATA LGPIO77 LGPIO76 LGPIO75 LGPIO74 LGPIO73 LGPIO72 LGPIO71 VSS LGPIO70 LGPIO67 LGPIO66 LGPIO65 VCC 1 PGM AGND XTAL2 XTAL1 XOSEL
Rev. 10/27/2000

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